1. Field of the Invention
This invention relates to, for example, a NAND flash memory, and more particularly to a semiconductor memory device capable of storing multilevel data in a single memory cell.
2. Description of the Related Art
In a NAND flash memory, all of or half of a plurality of cells arranged in the column direction are connected in series to constitute a NAND cell. The drain side of each NAND cell is connected via a select gate to the corresponding bit line. Each bit line is connected to a write and a read latch circuit. Data is simultaneously written into or read from all of or half of the cells arranged in the row direction. With the recent trend toward larger memory capacity, a memory which stores 2 bits or more of multilevel data into a single cell has been developed (for example, Jpn. Pat. Appln. KOKAI Publication No. 2004-192789).
In a multilevel memory, writing data into an adjacent cell causing a problem: the threshold voltage of the cell in which data has already been written rises as a result of the coupling between the floating gates (FG-FG) of the two cells. Accordingly, the following method has been proposed: for example, in the case of a cell which stores 3 bits using 8 levels, first, 3 bits of data are written to a lower verify level than the original verify level, and then the cells adjacent to this cell are written into. Thereafter, the preceding cell is written into to the original verify level. However, the writing of data into the preceding cell cannot be completed unless data to be written into the adjacent cells (or data in the adjacent cells) has been determined. Therefore, all the cells in the NAND cell have to be written into. Accordingly, a semiconductor memory device capable of suppressing a fluctuation in the threshold level of a cell already written into by writing data into adjacent cells has been desired.